Semiconductor device and fabricating method thereof

ABSTRACT

A semiconductor device and fabricating method thereof in which a lightly doped drain junction is graded using a diffusion property of dopant implanted in heavily doped source/drain region are disclosed. An example semiconductor device includes a gate electrode having a gate insulating layer underneath and disposed on a semiconductor substrate; a pair of lightly doped regions separated from each other in the semiconductor substrate and aligned with the gate electrode; a pair of heavily doped regions separated from each other in the semiconductor substrate and partially overlapped with the pair of the lightly doped regions, respectively; and a pair of diffusion source/drain regions enclosing the pair of the lightly doped regions therein.

RELATED APPLICATION

This application is a divisional application of U.S. application Ser.No. 11/021,056 filed on Dec. 23, 2004, which claims the benefit ofKorean Application No. P2003-0096991 filed on Dec. 24, 2003, which ishereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device, and moreparticularly, to a semiconductor device and fabricating method thereofin which a lightly doped drain junction is graded using a diffusionproperty of dopant implanted in heavily doped source/drain region.

BACKGROUND

Generally, the double diffused drain (DDD) structure has been used toimprove the hot carrier effect and the like of a semiconductor devicehaving a channel length greater than 0.35 μm. Such a device is notconcerned about breakdown voltage (BVDss) between source and drain aswell as roll-off of threshold voltage.

More recently, as channel length is shortened to achieve a high degreeof integration in semiconductor devices to raise the short channeleffect, the DDD structure is being used less. However, it isadvantageous for a low power device to have high threshold voltage andBVDss in securing junction leakage. As a result, the DDD structure isemployed in part. Yet, the short channel device still has theabove-noted difficulty in employing the DDD structure. For instance, atransistor as a low power device having small leakage current tends toemploy the LDD (lightly doped drain) structure instead of theconventional DDD structure to enhance the short channel effect due tothe reduced channel length. As the junction configuration is modified,the breakdown voltage between source and drain is lowered. This may beexplained as follows. When the LDD dopant increases, a junction betweenN-type LDD and a P-type well is abruptly formed to increase leakage fromthe junction region. Meanwhile, the known process of implantingadditional P-type dopant is mainly used in improving leakagecharacteristic and capacitance by grading a junction profile, not in theLDD region but in the source/drain region.

FIG. 1A is a cross-sectional diagram of a known semiconductor devicehaving a double diffused drain (DDD) and FIG. 1B is a cross-sectionaldiagram of a semiconductor device having a lightly doped drain (LDD).Referring to FIG. 1A, an STI layer 16 and an n-well or p-well 11 areformed on a semiconductor substrate. A gate oxide layer 12 is formed 30Å thick on the substrate, and a polysilicon layer 13 is deposited overthe substrate. A gate 13 is then formed by patterning the polysiliconlayer by photolithography. Subsequently, a PMOS or NMOS DDD region 14 isformed in the N- or P-well 11 by ion implantation. A sidewall spacer 18is provided to the gate 13 by depositing a nitride layer over thesubstrate and by etching back the nitride layer. Subsequently, ionimplantation is carried out on the substrate using dopant of As and Pions to form source and drain regions 15 and 19, and silicidation iscarried out on the substrate to form a Co-silicide 17 layer on the gate13 and the source and drain regions 15 and 19.

Referring to FIG. 1B, a process of fabricating a semiconductor devicehaving the LDD structure is similar to that of fabricating thesemiconductor device having the DDD structure in FIG. 1A, except forminga PMOS or NMOS LDD region 24 instead of forming the PMOS or NMOS DDDregion 14 in FIG. 1A by ion implantation. However, the short channeleffect still takes place in case of applying the DDD or LDD structure tothe known low power device. Moreover, a high electric field is appliedto the LDD region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional diagram of a known semiconductor devicehaving a double diffused drain (DDD).

FIG. 1B is a cross-sectional diagram of a semiconductor device having alightly doped drain (LDD).

FIG. 2 is a cross-sectional diagram of an example semiconductor devicehaving an LDD region enclosed by a diffusion source/drain region.

FIGS. 3A to 3F are cross-sectional diagrams depicting an example methodof fabricating a semiconductor device having an LDD region enclosed by adiffusion source/drain region.

FIG. 4 is a graph of a breakdown voltage between source and drain.

FIG. 5 is a graph for showing short channel effect enhancement in theexample semiconductor device described herein.

DETAILED DESCRIPTION

In general, the example apparatus and methods described herein provide asemiconductor device and fabricating method thereof, in which an LDDjunction is graded using phosphorous dopant diffusion of a source/drainregion and by which a roll-of characteristic of threshold voltage isenhanced as well as BVDss.

More specifically, an example semiconductor device includes a gateelectrode having a gate insulating layer underneath a semiconductorsubstrate, a pair of lightly doped regions separated from each other inthe semiconductor substrate to be aligned with the gate electrode, apair of heavily doped regions separated from each other in thesemiconductor substrate to be partially overlapped with a pair of thelightly doped regions, respectively, and a pair of diffusionsource/drain regions enclosing a pair of the lightly doped regionstherein, respectively. Preferably, a pair of the diffusion source/drainregions are heavily doped with additional dopant, which is preferablyphosphor (P). More preferably, junction profiles of the lightly dopedregions are graded due to lateral diffusion of the additional dopant.

An example method of fabricating a semiconductor device includes forminga gate electrode having a gate insulating layer underneath on asemiconductor substrate, forming a pair of lightly doped regionsseparated from each other in the semiconductor substrate to be alignedwith the gate electrode, forming a spacer to a sidewall of the gateelectrode, forming a pair of heavily doped regions separated from eachother in the semiconductor substrate to be partially overlapped with apair of the lightly doped regions, respectively, heavily doping theheavily doped regions with additional dopant, and diffusing theadditional dopant in a lateral direction toward the lightly dopedregions to form a pair of diffusion source/drain regions enclosing apair of the lightly doped regions therein, respectively. Preferably, theadditional dopant is phosphor (P), and, preferably, the additionaldopant is diffused to enclose a pair of the lightly doped regions toavoid a double diffused drain (DDD) structure. Preferably, junctionprofiles of the lightly doped regions are graded due to lateraldiffusion of the additional dopant and, preferably, the method furtherincludes the step of forming a silicide layer on the gate electrode anda pair of the heavily doped regions.

The example semiconductor device described herein may be used to improveBVDss, which was degraded by high electric field impression on thesource/drain region of the LDD semiconductor device and to improve theshort channel effect.

In the example semiconductor described herein, an LDD region is enclosedby P-type dopant using lateral diffusion of the P-type dopant added to asource/drain region, whereby the BVDss characteristic and short channeleffect are improved to enhance a process margin.

In the examples disclosed herein, P-type dopant is implanted in asource/drain region of a device applicable to a low power device and anLDD region is enclosed by the added P-type dopant using lateraldiffusion of the P-type dopant. In doing so, the implantation energy anddopant are optimized to form a graded dopant profile of the LDD regionto reduce an electric field impressed on the LDD junction, and thedopant profile is graded by lowering a junction depth of the LDD regionto prevent the short channel effect and to improve a roll-ofcharacteristic of threshold voltage. In particular, the examplesdescribed herein may be used to implement a MOS transistor, of whichroll-of characteristic of threshold voltage and BVDss characteristic areimproved by using P-type dopant diffusion after forming a gate sidewallspacer.

The examples described herein utilize the 0.18 μm standard CMOS processand may be fabricated using the operations described below. First, agate is formed 2,500 Å thick. N or P-type LDD is formed. A sidewallspacer is provided to the gate. As ion implantation is carried out toform heavily doped source and drain regions. P-type dopant is heavilyre-implanted to form a diffusion source/drain region. The LDD region isenclosed by the P-type dopant using lateral diffusion of the P-typedopant by optimizing a dose and implantation energy of the P-typedopant.

FIG. 2 is a cross-sectional diagram of an example semiconductor devicehaving an LDD region enclosed by a diffusion source/drain region.Referring to FIG. 2, a field oxide layer 36 is formed on a P- or N-typesingle crystalline semiconductor substrate to define an active area foran N or P-well 31. A gate oxide layer 32 is formed on the active area ofthe substrate by oxidation. A gate electrode 33 of polysilicon is formedon the gate oxide layer 32. LDD regions 34 lightly doped with dopant areformed in the active area of the substrate to be aligned with the gateelectrode 33. An insulating layer spacer 38 is provided to a sidewall ofthe gate electrode 33. Source and drain regions 35 heavily doped with Nor P-type dopant are formed in the active area of the substrate to beadjacent to the LDD regions 34, respectively, using As impurity ions,and additional P-type dopant is implanted in the source and drainregions 35 to enclose the LDD regions therein, respectively. ACo-silicide layer 37 is formed on the gate electrode 33 and the sourceand drain regions 35 only.

FIGS. 3A to 3F are cross-sectional diagrams depicting an example methodof fabricating a semiconductor device having an LDD region enclosed by adiffusion source/drain region in which the semiconductor device is a MOStransistor. Referring to FIG. 3A, a device isolation layer 36 is formedby a shallow trench isolation (STI) process in a field area on asemiconductor substrate to define an active area therein. In this case,the semiconductor substrate is an N or P-type single crystallinesemiconductor substrate. A P or N-well 31 is formed in the active areaof the semiconductor substrate. Ion implantation for threshold voltageadjustment is carried out on the semiconductor substrate. A thin oxidelayer 32 is formed 30 Å thick on the active area of the semiconductorsubstrate. A polysilicon layer 33 is formed 2500 Å thick on the thinoxide layer 32.

Referring to FIG. 3B, the polysilicon layer 33 is patterned byphotolithography to form a gate 33. LDD ion implantation is carried outon the substrate to form LDD regions 34 to be aligned with the gate 33using the gate 33 as an LDD ion implantation mask.

Referring to FIG. 3C, an oxide layer 8 is deposited 1,000˜1,300 Å thickover the substrate.

Referring to FIG. 3D, the oxide layer 8 is etched to remain on asidewall of the gate 33 including the gate oxide layer 32 only to form asidewall spacer 38. Source/drain ion implantation is carried out on thesubstrate to form N+ or P+ source and drain regions 35. In doing so, thesource/drain regions 35 are aligned with the gate 33 and partiallyoverlapped with the LDD regions 34, respectively.

Referring to FIG. 3E, additional P-type impurity ion implantation iscarried out on the substrate to heavily dope the source and drainregions 35 with P-type dopant. Hence, P-type diffusion source/drainregions 39 are formed using lateral diffusion of the P-type dopant.

Referring to FIG. 3F, a Co layer is formed 90 Å thick over thesubstrate, and a TiN layer is stacked 150 Å thick on the Co layer. Firstannealing is carried out on the substrate to form a silicide layer onthe gate and the source and drain regions 39. The Co and TiN layersfailing to react are removed, and second annealing is carried out on thesubstrate to complete salicidation.

Namely, to implement a lower power device of a short channel devicebelow 0.18 μm, P-type dopant is additionally implanted into the N+source and drain regions 35 to form the P-type diffusion source anddrain regions 39, and a junction profile of the LDD region 34 is gradedusing the diffusion property of the P-type dopant. As a result, theexamples described herein may be used to raise BVDss to enhance leakagecurrent.

FIG. 4 is a graph of a breakdown voltage (BVDss) between source anddrain, in which ‘Ids’ indicates drain saturation current. Referring toFIG. 4, a curve—A indicates an increment of BVDss in case of the new LDDstructure according to the present invention.

FIG. 5 is a graph depicting short channel effect enhancement in theexample semiconductor device described herein, in which ‘Vt1’ indicatesthreshold voltage. Referring to FIG. 5, enhancement of short channeleffect is shown in case of the example LDD structure. Accordingly, inthe examples described herein, the junction profile of the LDD region isgraded to raise the breakdown voltage between the source and drain,whereby the leakage current in the off-state of the MOS transistor canbe enhanced. Additionally, the example semiconductor device and methoddisclosed herein enhances the roll-off characteristic of the thresholdvoltage of the related art DDD structure. Still further, the examplesemiconductor device and method described herein applies the P and Coimplantation to control the profile of the LDD region.

While the examples herein have been described in detail with referenceto example embodiments, it is to be understood that the coverage of thispatent is not limited to the disclosed embodiments, but, on thecontrary, is intended to cover various modifications and equivalentarrangements included within the sprit and scope of the appended claims.

1. A semiconductor device comprising: a gate electrode having a gateinsulating layer underneath and disposed on a semiconductor substrate; apair of lightly doped regions separated from each other in thesemiconductor substrate and aligned with the gate electrode; a pair ofheavily doped regions separated from each other in the semiconductorsubstrate and partially overlapped with the pair of the lightly dopedregions, respectively; and a pair of diffusion source/drain regionsenclosing the pair of the lightly doped regions therein.
 2. Thesemiconductor device of claim 1, wherein the pair of the diffusionsource/drain regions are heavily doped with additional dopant.
 3. Thesemiconductor device of claim 2, wherein the additional dopant isphosphor (P).
 4. The semiconductor device of claim 2, wherein junctionprofiles of the lightly doped regions are graded due to lateraldiffusion of the additional dopant.